Last modify 26 January 2009.
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An actual photograph of the USA Tomy Tutor internals is on the Photographs page, in the "Disassembling the Tutor" section.
It's definitely worth comparing the Tutor's architecture with the TI 99/4A's; check out our analysis.
8x16Kbit NEC (probably DRAM), D416C-2, 8325D5009. 16K total, expands to 64K. The RAM is wholly owned by the 9918ANL "VDP" video chip (see below), and the CPU must access it through the VDP's I/O ports (very inefficient, same arrangement as the TI 99/4A). Port access resides in the CPU's $E000 iospace range; check out the Memory Map.
(Thanks to Raphael Nabet for various clarifications.)
The Tomy Tutor's CPU is the NMOS 16-bit TMS 9995NL, a descendant of the TMS 9900 in the 99/4A and equivalent to the 9995 in the 99/8 (thus, henceforth 9995). The 9995 includes on-chip 256 bytes of RAM (analogous to $8300 page in the TI-99/4A memory map), a timer function, a clock generator, seven prioritised hardware and sixteen software (XOPS) interrupts, a 16-bit instruction set (including signed integer multiplication and division operations), ability to juggle multiple register blocks in main RAM, serial I/O via communications register unit (CRU) and 16 on-chip flags. It resides in a 40-pin DIP and is powered at 5V, with a maximum address space of 64K (16 address lines and 8 data lines). The CPU runs off an external 10.738MHz clock (see the schematic), but divides it by four to run at approximately 2.7MHz. This divided clock is also exported on the CLKOUT pin for use by other devices.
It is important to note the 9995 is truly 16-bit despite presenting only eight data lines: instead of a direct 16-bit data bus access, the 9995 executes two 8-bit accesses to memory and internally turns them into the CPU's standard 16-bit word. All words are restricted to even address boundaries, i.e. the most significant 8 bits reside at even addresses and the other eight at odd addresses. Any memory access involving a full word directed to operate on an odd address will actually access the word at the address minus one. Both byte and word operations are supported in the instruction set. As an aside, this "muxed data bus" approach is similar to that used by the 9900 in the 99/4A. The 9900 is connected through a 16-bit bus to its 256 bytes of CPU workspace (like the 9995 has to its internal RAM), and interfaces to the rest of RAM through a 16-bit-to-8-bit multiplexer. The only significant differences are that the system ROM is directly attached to the 16-bit bus (not so in the Tomy), and that there are no direct byte operations available to the 9900 under this design (all access is effectively by word).
The 9995 has three internal registers accessible to programmers: the PC (program counter), ST (status register), and WP (workspace pointer). The PC is a 15-bit counter containing the word address of the next instruction to be fetched; the ST maintains the current state of the arithmetic overflow flag and interrupt mask level, as well as the result of programmatic comparisons, in its 16 bits; and the WP is a pointer to 16 words of RAM used as psuedoregisters for indexing, memory addressing, and calculations (the 9995 accesses individual words in the workspace pointed to by WP by doubling the index to the word, adding that to the WP (which is forced to a 15-bit quantity by setting the highest bit to 0), and executing a fetch for the result). The use of the WP/PC pairs in the 9995 memory map makes interrupt-triggered context switching at the processor level easy to manage, although there is no known software for the Tomy that takes advantage of this sophisticated capability.
The 9995 improves on its predecessor with its (at the time) advanced prefetch and poststore capabilities, essentially a primitive out-of-order execution path allowing the CPU to order reads and writes more efficiently. It can read several opcodes ahead in the execution stream while the core is processing, and may execute that instruction before writing out the last instruction's result. The 9995 is also capable of DMA sharing with external devices, triggered by placing the 9995 in "hold" state through the HOLD pin, which will allow the external device to access memory over the address and data lines until it releases the HOLD line, at which point the 9995 will resume operation. In addition, the 9995 has the ability to diagnose illegal instructions and do user-defined operations with them, up to and including exception handling and software-defined instruction handlers -- allowing future instructions to be emulated in software now and in hardware in later editions of the chip (the MID interrupt). Sadly, none of these facilities are leveraged at all by the Tomy BIOS. These facilities make the 9995 an amazingly powerful, flexible CPU (and an enigma as to why such a sophisticated hunk of silicon was chained to a machine intended for so mundane a purpose as a toy computer).
Video Chip "VDP"
TMS 9918ANL, similar to the 9918A, the chip in the TI-99/4 series, the Coleco Adam, and the Sord; same as the one in the 99/8. The 9918ANL runs off the same 10.7MHz external clock utilised by the 9995 CPU, but it divides it by three for a 3.58MHz internal speed, which is used to encode colour into the composite output signal and is also used by the SN76489AN sound chip (see the entry on the CLA and DCSG). Altering this clock speed will probably cause picture degradation or roll depending on the output viewer. Thanks to Jeff White for the explanation.
The 9918ANL is capable of addressing up to 16K of dedicated video memory (in this case, all memory in the Tutor is VDP RAM), generating up to a 256x192x16 video image with a user-configurable border. There are two separate versions for NTSC 60Hz and PAL 50Hz (the PAL version, presumably in the UK Tutors, having the 50Hz refresh rate and a slightly different palette). The VDP is mapped into the 9995 addressing space starting at $E000 using only two I/O ports (argh!), which makes direct access to its registers, not to mention VDP RAM itself, maddeningly over-complicated. To speed sequential memory access, the VDP RAM pointer is automatically incremented on each VDP RAM read or store. As the VDP has sole and exclusive access to its memory, it is also responsible and carries support for performing memory refresh as well.
There are four official screen modes on the 9918ANL, though the Tomy OS
allows no control over this to the user, and only two of the screen modes
are in fact even supported. Mode 0 refers to the standard
32x24 text mode (used primarily in Tomy BASIC), with character images
built from an 8x8 character cell table, and character colours based off
a 32-byte colour table controlling groups of eight characters at once
(which can be modified en bloc from BASIC using the
COLOR keyword, or more granularly using
trickery). Sprites are possible but there is no support in BASIC for them
(although there are ways around this :-). Mode 1 is a 40x24 text mode without
sprites using 6x8 character images, but it is not supported by the Tomy OS.
Mode 2 refers to the 256x192x16 high-resolution screen (used in
GRAPHIC mode and GBASIC), which is composed from 768 8x8 character cells
which contain independent bit patterns and up to two colours per 8x1 region
in each cell, along with sprite capabilities. Mode 3 refers to the 64x48x16
medium-resolution "multicolour mode" allowing 4x4 pixel blocks with
individual and exclusive colour control, but it is not supported by the
Tomy OS either.
There are also four undocumented modes on the 9918ANL (and 9918A) allowing split pattern generator effects, among other tricks, but they are not directly leveraged on the Tutor.
The 9918ANL supports up to 32 simultaneous on-screen sprites, providing no more than four are on any one scan line; each sprite can be either 8x8 or 16x16. The Tomy OS gets around the scan line limitation by limiting the user to only four sprites total. All sprites controllable in GBASIC and GRAPHIC mode are 16x16, additionally enlarged to 2x pixel size. The sprite coordinate system supported by GBASIC and GRAPHIC mode seems to have no support for the Early Clock bit (see the GBASIC Keywords list for how sprites are controlled programmatically).
The organization of the 9918ANL VDP RAM is important and worth reading, since other than the 9995's 256-byte RAM, that's all the memory the Tutor has!
ROM and Cartridge Port
Cartridge port sits above the ROMs; superficially similar to, of all things, the VIC-20 cartridge port (although of course the pinout is all wrong). Cartridges look similar, too, but of course this is only skin deep.
The American Tutor has two 28-pin ROMs, 32K in one and 16K in the other for a total of 48K ROM. (The box insists only 32K, which is probably based on the early Pyuuta and Grandstand Tutor systems which lacked a BASIC ROM.) Both the Pyuuta and the Pyuuta Mk II have single ROMs; the Pyuuta has the original 32K firmware and the Pyuuta Mk II has the later American firmware.
The Tomy BIOS (my term) resides in ROM 1 (labeled "Tutor-1" on most American Tutors I've seen and the Pyuuta Mk II). This is a 32K unit (my serial: 135 RA, 8333G46) and contains the lowest level routines used by the Tomy OS, including the system jump table, title screen, menu, cartridge library routines, GRAPHIC mode code and GBASIC. On the later firmware of the (presumed) UK late model Tutor, USA Tomy Tutor and the Pyuuta Mk II, GBASIC has been bowdlerized into a smaller variant to make room for a full GPL interpreter (although there is no GPL for the Pyuuta Mk II to run because it lacks the second ROM). The BIOS is 100% 9995 machine language and is tremendously fast. I have no idea what version of the BIOS lurks in the original UK Grandstand Tutor.
On the Pyuuta Mk II and the Tomy Tutor, but not the Pyuuta, GBASIC and the MONitor seem to get banked out when a cartridge is installed (in fact, the MONitor is entirely inaccessible; the user is dumped back into the menu). This behaviour is still being investigated and is probably controlled by the Custom Logic Array. On the Pyuuta, G-BASIC does not seem to be affected.
The 16K ROM 2 (my serial: 3G1, 3128C75) contains the GPL-based Tomy BASIC ROM, which based on analysis seems to be a modified port of TI Extended BASIC (read our analysis). Unlike the TI 99/4A, which was hobbled by maddeningly slow serial access to its GROMs, there are no "GROMs" per se in the Tutor, and the BASIC ROM is accessed like any other ROM as fast as the bus will permit. Thus, although not as speedy as a fully native system, Tomy BASIC outruns TI BASIC by a large margin.
ROM 2 has only been found in the USA Tomy Tutors, although a review I have on file suggests upgraded UK Tutors (not original Grandstand Tutors) have it also. Banking registers in the CPU's iospace, probably provided by the Custom Logic Array, are used to manipulate its presence and replace it with a cartridge ROM for execution when desired (but unlike the situation with GBASIC, this behaviour is transparent, and BASIC is not locked out when a cartridge is installed and not presently banked in). On the Pyuuta Mk II (which lacks ROM 2 despite having a BASIC option in its menu), it seems that the cartridge maps there directly (but it's not executable GPL code, so the machine inevitably crashes; see our description). This difference in the CLA allows the BASIC-1 cartridge to function, basically ROM 2 in an external case. It will not work on a Pyuuta.
Custom Logic Array and the SN76489AN Digital Complex Sound
The Custom Logic Array, as I've dubbed it, is a collection of various small logic arrays responsible primarily for mangling, er, managing the Tutor's complicated banking logic (particularly when a cartridge is present). Parts of this strategy have been decoded and appear in the Memory Map.
At the top left of the CLA (in the American Tutor) is the Texas Instruments SN76489AN DCSG "Digital Complex Sound Generator" controlling the Tutor's audio output, a very well-known and frequently utilized sound chip offering three simultaneous square-wave tone generators and one noise generator, featuring independent 16-level volume controls on each generator and two separate noise generation systems. Each tone generator contains a 10-bit frequency register computed from an external clock (actual generated sound frequency = 3.58MHz/(32*n) where n is the 10-bit frequency register; this clock seems to be the same one the 9918ANL uses); the sound output is generated by loading the frequency register into a ten-stage tone counter, decremented at a rate determined by the system frequency divided by 16. When this counter reaches zero, a "borrow" signal reloads the counter and toggles the frequency flip-flop. This flip-flop is fed through the attenuator, controlled by its own 4-bit register; each bit within the attenuator register selects a different weight for reduction (bit 0 = 16dB, 1 = 8dB, 2 = 4dB and 3 = 2dB, with bit 3 being MSB). Multiple bits may be active for intermediate values, but if all are selected, the voice is effectively muted.
As for the noise generator, the DCSG generates either "periodic" or pure white noise, selected by a single feedback control bit. Noise is generated on-chip using a shift register with an XOR feedback network (and a safety system that prevents the shift register from being locked at zero). In periodic mode, a regular pulsed pattern with a duty cycle of 6.25% is generated based on the frequency register (see below); in white noise mode, a pseudorandom full-spectrum pattern is emitted instead. The frequency of the noise generator is determined by a 2-bit register which selects from clock/512, clock/1024, clock/2048 or the output of tone generator 3 (bit pairs 00, 01, 10 and 11 respectively).
The layout and presumably the functions of the CLA chips are different in the various Tutor and Pyuuta incarnations and may even differ slightly between revisions of the Tutor, as two of my American Tutors have slightly different discrete logic chips but no apparent change in function. The Pyuuta Section has photographs of the CLA chip layouts on those units, which are all different from the Tutor's. As mentioned above, even the Pyuuta and Pyuuta Mk II differ.
Not Shown Here
Many of these items are shown on the Photographs page.
This is a schematic of the Tomy tape cable, the hardest thing to find -- but pretty simple to build. It consists of a 5-pin DIN male plug terminating in two 1/8" monaural male headphone plugs.
Looking at the 5-pin male DIN head-on, numbering pins starting at the lower right and going clockwise:
According to Dan Eicher, this cable is the same as the one for the TRS-80 Model 100. This computer is not as obscure, but it's up there. Nonetheless, if someone is selling Model 100 equipment, see if they will sell you this cable as an item, since the few Tutor owners I know of are all after them.
Incidentally, as mentioned above, there is nothing special about the Data Recorder -- it's just a cassette deck with no particular distinction other than colour coordination. A regular cassette recorder will suffice, unlike things like Commodore Datasettes that really do have special logic inside.
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One important use for the I/O port is, of course, peripherals. Bob Abercrombie, an enterprising member of the Tomy Tutor User Club, managed to get not only information on how to connect devices to the Tomy Tutor, but how to construct a working printer interface. Thanks to James Host, who provided me with a photocopy, I have scanned it, converted it to .pdf, and made it available.
Please be nice to the server -- to force you to download the .pdf and read it locally, it is zipped. Unzip it, read it and warm up your soldering iron (347K).
Essentially, what the interface is doing is converting the I/O port into a Centronics printer port. Note that the Tutor has always been able to drive the printer if the hardware was present; the 9995 memory map shows where the Centronics port registers exist in memory, and Tomy BASIC can drive the printer by itself with the LLIST and LPRINT commands. The hardest part is finding the connector; I believe (but have not proven) that most of these DigiKey equivalent parts will work. If you know better or can verify, please say so.
Should you wish to try your hand at something bigger, here is the pinout for the I/O port (28K). The I/O port has 50 pins, numbered as you look at the I/O port from the back with the cover off, left to right, alternating top-bottom (so the top leftmost pin is 1, the bottom leftmost is 2, then 3, 4, etc.). To help you with connections internally, the numbers should be silkscreened onto the board. Careful -- errant mistaken connections WILL DESTROY YOUR TUTOR.
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