Xetec Multiplexer Unit for Lt. Kernal Hard Drive
Return to Main Menu
Required Tools: Oscilloscope or Logic Probe (must detect Low, High & Pulse). A DVM, alone, won't help much.
Note: - Troubleshooting the Mux unit
assumes that you have already connected the Host Adapter
directly to the hard drive and determined that the system
operates properly without the Mux unit, and
- When the term "Host Adapter" is used
here, it should be understood that it includes the Commodore Host computer.
That means the Host Adapter is a simply an extension of the Commodore,
which is the unit that generates/receives SCSI commands & data to/from
the hard drive.
The Xetec Multiplexer (Mux) unit is
a straightforward designed system that divides access
control of up to four (4) Lt. Kernal Host Adapters to one
hard drive. The Mux is also designed to interface with up to
three other Mux units (total of four) providing hard drive control
by a maximum of 16 Host Adapters. The Lt. Kernal and Multiplexer
unit combination is the only system that offers the means of
connecting multiple Commodore 64 or 128 computers to one hard
All SCSI Data lines and Control lines are common-bus at the J2 through J5 connectors. For example, the SCSI Data bit, D0, is connected to pin 1 of each Host Adapter connector at J2 - J5 just like *I/O is connected to pin 17 of J2 - J5 connectors. This common-bus architecture, along with the few number of ICs in the Mux unit, means it's easy to build your own Mux prototype unit. Using the schematic as a guide, you won't need to duplicate the P1 connector circuitry, SC & SS feature or even provide a four-Host Adapter capability. Several people have built Mux prototype units for just two Host Adapters. Note: Mux IC U9 can be omitted, but don't forget to ground it's output to ICs U2, U6, U7 and U11.
Before looking at the logic, it's probably good to mention here that the first component to check would be the output of the onboard 5-volt regulator if you were having Mux unit problems.
The following information should assist you in troubleshooting and repairing any possible Multiplexer unit problem. While it helps to understand the eight SCSI Phases and Command Descriptor Block (CDB) formats, it is not necessary to have an in-depth knowledge of "SCSI" to troubleshoot the Mux unit. Refer to the schematic and Mux Timing diagram for more information. The following information covers:
- An initial test of the Mux unit
- A preliminary test between the Mux and Hard Drive
- Troubleshooting - Part One
- Troubleshooting - Part Two
- Special Note - SS & SC Jumpers
- General Tips
- Timing Diagram
Because the Lt. Kernal hard drive is a SCSI system, the Mux unit divides access control to the hard drive via the SCSI Bus control lines. These control lines are basically split into two groups. The first group is *BSY (Busy) and *SEL (Select) which are used to establish communications between a selected Host Adapter and the hard drive. The second group includes *I/O, *C/D, *REQ, *MSG and *ACK which control and define the type of communication that will take place. Until a Host Adapter and hard drive arbitrate a link to each other, the SCSI Bus is in a Free Phase (idle). While the SCSI Bus is free, the Mux unit continuously polls each Host Adapter, one at a time, to see if its *SEL flag is up meaning it wants use of the SCSI Bus. Don't get confused here - when the terms "raising the flag", "*XXX is active", etc., are used, it means that it is a logic Zero or Low. That is, the "*" in front of the SCSI control name means a logic Low is a logic True.
The Mux unit scans for Host Adapter SCSI Bus request indirectly via the Counter, U4 that is driven by the Clock, U3. This Counter and related circuitry must be running in order to be able to multiplex between different Host Adapters. To initially test the Counter for proper function:
1. Disconnect all data cables from the Mux unit and apply power-only to the Mux.
2. Check for counting (pulses) on pins 11,12,13 & 14 of U4
3. If not counting, check pin 10 of U3 - Clock (count rate approx. 0.6ms to 1ms).
4. If U3 is working but U4 is not counting, check pins 7 & 10 of U4 - should be High.
5. If pin 7 of U4 is Low, check D1.
6. If pin 10 of U4 is Low, check U5, U10, U7 and U8 - none are active at this point (more detail below).
7. Check schematic for additional details.
If the Clock & Counter are functioning, disconnect Power and connect Hard Drive (via cable). Power up Hard Drive and Mux unit. Now, recheck U4 (and U3):
1. If Counter (U4) or Clock (3) are not functioning, recycle power on drive or replace Drive and retest.
a. Only a faulty drive would produce Low *BSY (or *RST) and disable Clock at this time.
2. If Counter or Clock are still not functioning, check cabling and SCSI adapter board in drive enclosure for shorts especially on *BSY & *RST lines. There's no reason why simply connecting a powered-up drive would cause Counter to stop.
The next series of tests determine the proper functioning of the *BSY & *SEL lines between the Host Adapter, Mux unit and hard drive. Power down drive and Mux unit. Connect a Host Adapter to the Commodore including computer cabling (HIRAM & CAEC if C64 or Daughterboard and 10-pin ribbon cable if C128) then connect Host Adapter to Mux and the hard drive via cables. Power up the hard drive, then the Mux unit, then the Computer. At this point, if the system were working properly, the system would boot-up from the SYSGEN data already installed on the hard drive. However, since you're reading this, I take it that the system did Not boot-up with the Mux unit installed.
Here is a preliminary test to help you determine the extent of Mux unit problems:
1. With Mux and hard drive powered up, either power off the computer and then back on or, better yet, press computer Reset button while observing the hard drive:
a. What activity did you see on the hard drive LED (if your drive does not have a drive activity LED, install one)?
- If you can't install a drive LED, you'll have to Listen to the drive for Slew, Head movement, stepper motor, etc. - more difficult, but not impossible.
2. The purpose of the above, first-pass test is to determine if basic communication is taking place via the *BSY and *SEL control lines from the Host Adapter to the hard drive.
3. If there was no LED activity upon power-up (or Reset) or you didn't hear the drive heads move, go to Part One troubleshooting.
4. If there was LED activity (flashing), go to Part Two troubleshooting. The problem could be related to *BSY or *SEL, but LED activity would suggest other problems in the Mux unit.
Part One - troubleshooting:
No hard drive LED activity indicates there is no basic communication between the Host Adapter and hard drive. Therefore, you can trace through the Mux circuit in order to determine if the problem is on the Mux board or possibly in cabling. The test Configurations is to use one Host Adapter plugged into J2 on the Mux unit (marked Master (Slave 1)). Also, the following tests are easier to perform by pressing the computer Reset button, where indicated, compared to turning the computer on and off. Now, properly connect the Computer, Host Adapter, Mux unit and hard drive then apply power.
The very first thing that is suppose to happen is the Host Adapter sends a *SEL request (active Low) to the Mux unit:
1. J2, pin 20 goes to pin 5 of U8 and should go Low, (*SEL from Host) requesting control of the SCSI Bus. Press Computer Reset button to test.
- Note: The Host Adapter will set *SEL for a short period and then Time Out. That's why you may find it necessary to Reset the computer in order to cause the *SEL to set again.
- Note 2: U8 contains four buffers, one for each of the Host Adapter *SEL inputs (J2, J3, J4, J5). Each of these buffers has a control enable line that goes to pin 16 of J2, J3, J4 & J5 respectively. However, before you go nuts trying to figure out how the Host Adapters control these Enable pins, don't bother. Pin 16 on the Host Adapter's J1 connector is connected directly to +5VDC at RN1 source - always wired High. So, in a Multiplexer environment, each Host Adapter enables one of these U8 buffers.
2. U8 (pin 6) output is passed to pin 4 of U7. WHEN the Counter (U4) and Mux selector (U9) decodes to ZERO (~ every 10 milliseconds), pin 6 of U7 (W or *Q) goes High which latches U10, pin 5 High. The High at U10, pin 5 is inverted (Low) by U5, pin 6 and sent to pin 10 of U4 (Counter). This Low at pin 10 of U4 temporarily Halts counting (check schematic to follow flow).
3. The Counter halted at binary zero also does several things:
a. Sends Low to Host Adapter (enables Data flow) J2, pin 10 via U11, pin 15
- 'I just got your *SEL request', the SCSI Bus is available
b. Enables U2 8-bit Data flow to/from Host Adapter (J2) & hard drive (J1) via U2, pin 19
c. The above (a. - b.) have tested most of the ICs on the Mux board.
4. If you had plugged the Host adapter into J3 (Slave 2), the Counter (U4) would have stopped at a binary count of One and would have sent:
a. Low to J3, pin 10 via U11, pin 14
b. Enable (Low) to U2 8-bit Data flow to/from Host Adapter (J3) & hard drive (J1) - etc.
5. The *SEL from the Host Adapter has Only:
a. Enabled 8-bit DATA flow to/from Host Adapter and hard drive within the Mux
b. Sent Enable back to Host Adapter (enable its 8-bit Data flow at Host's U4)
c. However, both of these Data enables are Key to the next step - SCSI arbitration.
6. Sending this Mux-generated Host Adapter Enable (J2 pin 10) back to the Host Adapter means the Host Adapter can now go on with SCSI Bus communications. An often misunderstood point of grounding (or sending a Low) to pin 10 of the Host Adapter only means:
a. Enables 8-bit Data flow between the Host Adapter and hard drive, and
b. In a Non-Muxed setup, ground is applied to pin 10 by a grounding strap on the SCSI adapter board inside the hard drive enclosure (always hardwired Low).
Up to this point, has there been any SCSI Bus communications? NO! - Only a primitive hardware-handshake between the Mux and Host Adapter during a multiplexed time slot. However, during this brief time slot and when the Host Adapter is enabled (pin 10), the Host Adapter tries to grab the Bus by using the other Control lines. This is where we move to part two of troubleshooting.
Part Two - troubleshooting:
When the SCSI Bus is free and Host Adapter is enabled, Commands can be sent to the hard drive. Suppose that the enabled Host Adapter sends a command and wants to know if SCSI address Zero is a hard drive and if it is available. If the SCSI device is a hard drive (target) and it responds, the Hard Drive responds by raising its *BSY line letting the Host Adapter (initiator) know it's ready to dance. This is the point where SCSI communications begins.
When the hard drive raises its *BSY line, here's what happens in the Mux unit:
1. The active *BSY enters the Mux at J1, pin 24. When the drive's *BSY goes Low, it does Four things:
a. It disables the Clock via Diode D1 by grounding pin 13 of U3 (prevent U4 counting)
b. It also disables the Counter at pin 7 (U4) while maintaining the current binary count which in turn holds the current multiplexed Host Adapter decode.
c. It incidentally sends the *BSY to other attached Mux units via P1, pin 24
d. It finally sends the new, "yeah,
I want to dance", *BSY signal to the Host Adapter at J2,
pin 24 via U6, pin 15
- Did you see the connection between the Drive's *BSY at J1, pin 24 and the Host Adapter's *BSY input at J2, pin 24? This is directly connected in a Non-Muxed system.
e. Now, the Arbitration Phase of SCSI communications has successfully taken place and the SCSI Bus is Busy. The SCSI Bus will remain 'busy' until released by either the hard drive (target) or computer (initiator). This is also where you may have seen the first flash of the drive activity LED.
During this Busy state, other information must be exchanged between the computer and hard drive. The computer (via the Host Adapter) can send other commands, input/output Data, and check status or send other types of messages. These different SCSI Phases of communications are controlled by the second group of SCSI control lines.
Once the SCSI Bus is busy (*BSY), here's a list of control line combinations (Phases) that give you an idea of what's happening:
DATA OUT = *BSY Low and *MSG, *C/D & *I/O High
DATA IN = *BSY, *I/O Low and *MSG, *C/D High
COMMAND = *BSY, *C/D Low and *MSG, *I/O High
STATUS = *BSY, *C/D, *I/O Low and *MSG High
MEASSGE OUT = *BSY, *MSG, *C/D Low and *I/O High
MESSAGE IN = *BSY, *MSG, *C/D, *I/O Low
If just one of these Mux-buffered control lines is faulty, continued communications will cease, Bus times-out and the drive's *BSY goes High (Counter continues counting and Mux searches again). For example, the direction of Data flow between the Host Adapter and hard drive is controlled by *I/O (Input/Output). This signal is buffered by U1 in the Mux unit. You should already know that if U1 is defective, it could prevent the system Serial Number and Drive parameters (which are stored on the drive) from reaching the Host Adapter (DATA IN Phase). (This is the very first thing that's suppose to happen upon Host Adapter's Boot-up routines) In turn, this would cause the Lt. Kernal boot-up to abort (same result as the drive's *BSY line going High). This same situation could also happen if *I/O was working properly, but one of the eight Data lines was faulty in U2!
Here are the few remaining control lines to check in the Mux unit. As an initial test, these lines could be tested with the Mux removed from the system (i.e., Host Adapter, hard drive & cables removed - all below inputs and outputs in the Mux should be High is not connected in the system) and then system tested under active conditions later:
1. Since we already mentioned this one, *I/O enters from the hard drive at J1, pin 17 and goes to U1, pin 17 (input). U1 output at pin 3 goes to pin 1 of U2 (direction) and pin 17 of all Host Adapters connects (J2, J3, J4 & J5). And yes, the Host Adapter does drive against the output of U1, pin 3 (it's okay, small Source current). What would happen if pin 3 of U1 shorted to ground?
2. *C/D (Command/Data) is buffered by U1. Input from the hard drive at J1, pin 19 to U1, pin 13. Output at pin 7 of U1 to pin 19 of all Host Adapter connectors (J2, J3, J4 & J5).
3. *REQ (Request) is buffered by U1. Input from the hard drive at J1, pin 18 to U1, pin 15. Output at pin 5 of U1 to pin 18 of all Host Adapter connectors (J2, J3, J4 & J5).
4. *MSG (Message) is buffered by U1. Input from the hard drive at J1, pin 21 to U1, pin 11. Output at pin 9 of U1 to pin 21 of all Host Adapter connectors (J2, J3, J4 & J5).
5. Notice flow direction of 2. - 4. above are from hard drive to Host Adapter, but *I/O can be driven by either the Host Adapter or hard drive! Again, all of the above control lines can be repeatedly tested by simply pressing the computer's reset button.
6. *ACK (acknowledge) is buffered by U5. Input from pin 23 of all Host Adapter connectors (J2, J3, J4 & J5) to pins 12 & 13 of U5, output pin 11 of U5 to input pins 9 & 10 of U5. Output pin 8 of U5 to pin 23 of J1 & pin 23 of P1 (buffered twice because U5 is a NAND gate - inverted back to true logic). Also, the Host Adapter (*ACK) acknowledges the hard drive (not the other way around).
7. If 1. through 6. above seem good, suspect cabling or DB-25 connectors.
8. Again, all of the above control lines can be easily tested by simply repeatedly pressing the computer's Reset button and viewing the appropriate logic points.
Special Note - SS & SC Jumpers:
Many have asked about the purpose of the SS and SC jumper-pin connectors on the Mux circuit board. Simply stated, normal function of the Multiplexer unit does not use either of these two jumper-pin connectors and should be left disconnected! Some say SS & SC were for Testing while others speculated it was for Tape to Hard Drive backup. In any event, their circuit function is unclear, but this is what happens if you Jumper either set of jumper-pin connectors. Remember too that since the SS & SC functions are not normally used, the circuits described below could be the cause of an existing problem, which is causing the Mux to fail as an intended Multiplexer.
A jumper placed on SC grounds the Clock at pin 11-12 of U3 and disables the Clock. This means that the Counter (U4) can not count and, therefore, can not multiplex between attached Host Adapters. The term SC implies "Switched Clock" and may have been intended for external clocking (i.e., external cable and not jumper plug).
A jumper placed on SS enables the other half of U1 including four of its Buffers. However, shorting SS will disable the Multiplexer. The IC not completely explained in the above is this other half of U1. Since the jumper is not installed on the SS pins of the Mux board (which would Enable the other half of U1), the four remaining buffers are permanently set to a high impedance output state. This effectively takes them out of the functional description. However, by shorting SS, this is what happens:
Shorting SS enables (Low) U1 at pin 1 which enables the outputs of four internal Buffers of U1. These outputs are all individually connected directly to one of the four bit outputs of the Counter, U4. Therefore, if one of these Buffers outputs a Low, it disables the corresponding bit on the Counter that effectively changes the Decoded Multiplexer number. That is, if all of these four U1 buffers output Low, the Counter U4 is forced into Binary Zero - Slave 1. So, what drives these four normally-unused U1 buffers?
a. J1, pin 9 (hard drive - *Parity) connects to pin 2 of U1 which outputs on pin 18. Pin 18 of U1 is connected to U4, pin 14 (QA) and all other normally connected ICs.
b. J1, pin 10 (Grounded Low by the SCSI adapter board) connects to pin 4 of U1 which outputs on pin 16. Pin 16 of U1 is connected to U4, pin 13 (QB) and all other normally connected ICs.
c. J1, pin 12 (Grounded Low by the SCSI adapter board) connects to pin 6 of U1 which outputs on pin 14. Pin 14 of U1 is connected to U4, pin 12 (QC) and all other normally connected ICs.
d. J1, pin 25 (hard drive - *ATN) connects to pin 8 of U1 which outputs on pin 12. Pin 12 of U1 is connected to U4, pin 111 (QD) and all other normally connected ICs.
So, shorting SS only produces, at best, unusual switching between Slave 1 and Slave 2. However, this configuration no longer functions as the intended multiplexer of four Host Adapters and a hard drive. And, if you are considering building your own Mux prototype unit, there is no reason to include any of the SC and SS circuitry.
1. Under normal operating conditions, the Mux ICs do Not run Hot. If hot, suspect shorts or bi-directional signal flow at the same time. For example, if *I/O was stuck Low (DATA IN) on the Mux, but the Host Adapter was sending Data out (DATA OUT), more than IC U2 will smoke! Even if *I/O is operating properly, one bad Data bit Buffer inside U2 could cause overheating.
2. In the world of '74LS' series,
always look to open-collector designed ICs like 74LS38,
etc. for problems.
3. Only use a 74LS161A as a replacement
for U4 (not a 74LS161). The '161A' provides for asyncronus counter
halting via pins 7 and 10.
4. If ONE of the Host Adapter ports (J2, J3, J4 or J5) works and one or more ports don't, the problem can only be U6, U7 or U11 (single decode not working) or U4 is not properly counting.
5. Under normal operating conditions, the Mux unit should Not have jumpers installed in SS & SC.
6. Do Not, repeat, Do Not use Mux connector P1 as a Host Adapter port! The P1 connector is designed for inputs from other Mux units, not Host Adapters.
(Click HERE for HiRes (200K) view in New Window)In addition to showing how each Host Adapter is given exclusive access to the Hard Drive, the diagram also shows how one Host Adapter starts a SCSI Arbitration Phase with the Drive. If the Hard Drive does not receive a following valid CDB from the Host Adapter, the Drive releases *BSY and the Multiplexer continues scanning for requests from other Host Adapters.